1. Field of the Invention
The present invention relates to a manufacturing method of a patterned structure of a semiconductor device, and more particularly, to a manufacturing method using multiple and stacked conformal spacer layer to increase the pattern density of the patterned structure in the semiconductor device.
2. Description of the Prior Art
The development of semiconductor integrated circuit technology progresses continuously and circuit designs in products of the new generation become smaller and more complicated than those of the former generation. The amount and the density of the functional devices in each chip region are increased constantly according to the requirements of innovated products, and the size of each device has to become smaller accordingly. However, photolithography technology is used to form patterned structures in general semiconductor manufacturing processes. The size and the spacing between the patterned structures are limited by the exposure resolution minimum of the photolithography technology and hard to be further shrunk, and that becomes a bottleneck issue of the semiconductor technology. The sidewall image transfer (SIT) technology has be provided by the related industries for transferring patterns of the sidewall with size smaller than the exposure resolution minimum of the photolithography technology. However, it is still hard to manufacturing patterned structures with extremely small size and spacing and further higher pattern density.